NXP Semiconductors /LPC5410x /SYSCON /SYSPLLSSCTRL1

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Interpret as SYSPLLSSCTRL1

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MD0 (MDREQ)MDREQ 0MF0MR0MC0 (ENABLED)PD 0 (FIXED)DITHER 0RESERVED

DITHER=FIXED, PD=ENABLED

Description

PLL spread spectrum control 1

Fields

MD

M- divider value with fraction. MD[18:11] : integer portion of the feedback divider value. MD[10:0] : fractional portion of the feedback divider value.

MDREQ

MD reload request. When a 1 is written to this bit, the MD value is loaded into the PLL. This bit is cleared when the load is complete.

MF

Programmable modulation frequency fm = Fref/Nss with Fref = Fin/N 0b000 => Nss = 512 (fm = 3.9 - 7.8 kHz) 0b001 => Nss = 384 (fm = 5.2 - 10.4 kHz) 0b010 => Nss = 256 (fm = 7.8 - 15.6 kHz) 0b011 => Nss = 128 (fm = 15.6 - 31.3 kHz) 0b100 => Nss = 64 (fm = 32.3 - 64.5 kHz) 0b101 => Nss = 32 (fm = 62.5- 125 kHz) 0b110 => Nss = 24 (fm = 83.3- 166.6 kHz) 0b111 => Nss = 16 (fm = 125- 250 kHz)

MR

Programmable frequency modulation depth deltafmodpk-pk = Fref x k/Fcco = k/MDdec 0 = no spread 0b000 => k = 0 (no spread spectrum) 0b001 => k = 1 0b010 => k = 1.5 0b011 => k = 2 0b100 => k = 3 0b101 => k = 4 0b110 => k = 6 0b111 => k = 8

MC

Modulation waveform control 0 = no compensation Compensation for low pass filtering of the PLL to get a triangular modulation at the output of the PLL, giving a flat frequency spectrum. 0b00 => no compensation 0b10 => recommended setting 0b11 => max. compensation

PD

Power down.

0 (ENABLED): Enabled. Spread spectrum controller is enabled

1 (DISABLED): Disabled. Spread spectrum controller is disabled

DITHER

Select modulation frequency.

0 (FIXED): Fixed. Fixed modulation frequency.

1 (DITHER): Dither. Randomly dither between two modulation frequencies.

RESERVED

Reserved. Read value is undefined, only zero should be written.

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